Nanion Technologies

Low Capacitance Holder

The Low Capacitance Holder for the Port-a-Patch has been developed to reduce the capacitance of the recording system, thereby increasing the temporal resolution and the signal-to-noise ratio.

This reduction in capacitance is critical for experiments requiring increased resolution, e.g. recordings of small conductance ion channels with fast gating properties in a planar lipid bilayer or in the cell attached mode.

The capacitance of the whole system including a bilayer on the chip is approximatey 2.5 pF, compared to 6.5 pF for the standard Port-a-Patch. This corresponds to Irms values of 400 fA compared to 1.1 pA (gain: 1000 mV/pA, bandwidth: 3 kHz) for the Low Capacitance Holder and the standard Port-a-Patch.